// veriloga_dec2bin8,veriloga`include"constants.vams"`include"disciplines.vams"moduleveriloga_dec2bin8(vin,vout,vdd,vss);//vddistheoutputvoltagehighlevel//parameterrealvdd=5.0;//parameterrealtrise=0from[0:inf);//parameterrealtfall=0from[0:inf);//parameterrealtdel=0from[0:inf);inputvin;output[0:7]vou